2009 cpu development is limited to quickpath(hypertransport pipeline) at about 6 ghz. The scheme is slowed down by the speed of rams for storage of the quickpath data(ascii codes) streams. The easy trend of development is now obviously futile, because rastered pixel transfer has the least framebuffer size; and toolbar and taskbar needs cpu hardware functions defined on a quick click of the mouse for operating system built in.

The information technology is now clearly dependent on search engines and method of multimedia storage(analog bit stream of info from cameras and microphones). Even Faxed webpages are analog bit streams.

So, A/d and Risc with pwm and Fpu plus rams is the way the future cpu design has to go. Faxed webpage has the multimedia content, and the toolbar and taskbar are the cpu instructions. Apparently, then faxed webpage can replace ascii codes directly, if cpus has hardware asics(firmware in rams) functions to deliver analog data by automation of low level instructions scripted to run highly advanced data movements(packet switching).

Footnote:
Ascii codes are instruction codes first, then alphanumerical codes, then graphics codes in a table. Faxed webpages with toolbars and taskbars contains everything ascii codes have and more.

Current cpu designs are not efficient in analog data transfer because the design lack PWM(PLL plus waveform control) to do highest compression scheme such as PRML direct conversion? And A/D(analog to digital converters) to do mixed signal data compression and multiple data streams efficiently.

More footnote:
We have been using DSP designs for brainwave transmission efficiently for 5 years now, with bit stream over sampling to get rid of noise. Rams are on the same bus as cpu. Data transfer is done by antenna using different PLL clocks.