When DDR memory was proposed, semiconductor submicron lithography was not as advanced as today(0.065 micron). The bus frequency were 100/133 mhz, to be equivalent of 200/266 mhz, using leading edge and trailing edge of a clock cycle square wave for time division multiplexer data transfer. Since then the equivalent frequency is 800 mhz and beyond, but thru more parallel data processing virtual pipelines(time division multiplexers), not brute force high frequency clocks and multiplexers.

The real DDR bus has to be improved to speed up the computer. This is really needed in ASUS Eee Pc laptop and other Geode computers. what speeds up computers are cpu frequency, cache memory size, zero wait state to all the buses outside of cpu.

Wait state is the most important speed consideration. Wait state of one being an overhead of the posix packet size is slower than wait state of zero. If you use predictive branching for each clock cycle, one clock cycle wait state can make data processing, transfer rate really slow.

So now its real important time to redesign buses to take advantage of zero wait state for entry level computers with slower cpus.