For many years, since the invention at Bell Labs, semiconductors were made by alloying and processed by wet chemicals of oxidation and reduction. Respectable 10% yield went to 30%(polished surface), then 70%(reduced surface contamination after oxidation), then 90%(denude zone from outdiffusion during oxidation) now finally 100% yield(cmos instead of bipolar) by abandoning wet chemicals and alloying and use ion deposition and dry chemicals.

Now,with the prospect of over 1 billion transistors on each cpu; silicon computers will have over 20 mB of srams and flash(raif data compression) on one chip.

This required many technologies:
Ion deposition
Phase change(90 degree shift) mask lithography with dye laser
Flip chip connections(USB and power)
RF radio channel bus
Tuned gate(RF antenna on gate capacitance) cmos transistors
Ultra low core voltage(10,000 micro volts)
Function keys for instant-on asic on risc handling analog/digital mixed signals(extended multicored ARM)

Still, there will be more added to make computing better. Eventually wafer scaled computers will take over motherboards(assembled chipsets) to produce cheaper but more powerful computers. With multiple wafer computers, stacked wafers can communicate by RF radio channels.

The name of this game is still no wire longer than 0.1 of an inch? Cray Research super computers started with no wire longer than 36 inches. Sometimes, RF antennas are fingers of surface wave transmission, right next to each other?

As linewidth reduces, the voltage that can be supported is reduced by the law of dielectric constant(oxide). Or 400 volts per mil(One thousandth of one inch). Rough order of magnitude is 130 nm for 1.2 volts. 45 nm for 0.4 volts.

This means even if you are working with ultra low 0.2 volts(core voltage), the input and output voltage has to be pulled up to 1.2 volts or 5 volts with darlington transistor to conform to external circuits.

However, to work without fans, 0.2 volt core voltage will have to be reduced 7 times(experience proven). to run at maximum speed(striplined circuit and RF radio bus necessary).

This is the reason, you hear cpus that run 14 watts now run at 2 watts. Those that are using hibernation to reduce power still had to run at reduced duty cycle and speed(sometimes half the designed frequency). Those running at 7 times reduced core voltage can run at maximum speed full time(no hibernation or suspend on chip select)

1 ghz frequency required stripline circuits. Strip is a straight line of circuit. Electrons do not turn directions. Standard electrical circuit analysis applies. Stripline circuit has to be terminated to prevent back reflection noises, depending on wavelength nodes.

So, in semiconductor circuit designs, stripline circuits end with RF antennas to transmit high frequency signals by radio waves or surface waves.

Cadence mask design software uses high level design language to place 7400 standard cells. But they have to be streamlined to straight line connections. Any signal turning corners had to be replaced by antenna design, not hard wired connection.

So, you can see why AMD cpus are slower in clock frequency than Intel cpus. But both of them still not using RF antennas. They can not break the 4 ghz barrier. Electrons will collide and pile up to create tremendous heat(red hot 1000 degrees C). The heat will distribute in the chip. And reduced frequency will survive with the cooling fan. Reduce duty cycle helps, and reduced core voltage will help a lot.

Beyond that, Cadence software had to use Spice to redesign propagation delays on length of wire. Propagation delays of each transistor in series.

Until design software is improved, we will always have a frequency barrier. But 70 ghz may be our target to improve design software.

People are still fascinated with linewidth narrower yet.

But when we design RF antennas on the top of dielectric gates, the contact has to be shaped to roof top antenna design(quarter wavelength of clock frequency). Linewidth has to be a hundred times narrower than the active area linewidth.

The way we have to do it is to use narrower Polaroid filters. So that fine structure are a hundred times smaller than active transistor features.

Polaroid filter may have to be rotated 360 degrees to allow finer linewidth placement below the mask.

Semiconductor industry is way behind in technology so far. And steppers may give way to whole wafer lithography machines.

"Polaroid filter"

Is that the new instant, no developing lab required, type filter?

Perhaps you mean "polarizing filter"?

Also, if you rotate something 360 degrees - isn't it pointing in the exact same position as if it hasn't been rotated?

Its a simple explanation for lithography technology. where dye laser output goes thru mask then Polaroid filter of slits. Slit linewidth determines the true linewidth not mask linewidth, not confused with its polarising effect. Linewidth of slit allows linewidth of light intensity to shine thru and reach photo resist not photographic film.

The Polaroid filter is usually turned 90 degrees for masks of integrated circuits in a two stepped process. But for RF roof top type of antennas, the antenna elements are slanted at 15 or 30 degrees. So, Polaroid filter should be capable of turning 360 degrees on the lithographic equipment.

If you had experience with Polaroid filters then you know 360 degrees turning with two Polaroid filters can control light intensity thru the two polarising filters. We are only using one Polaroid filter. Mechanical engineers use a pair of Polaroid polarising filters to study strain in mechanical parts, for stress analysis.

In lithography, it has been a life saver for linewidth control over the last 10 years without spending more money other than using finer and finer linewidth of slits filters. They are cheap and controls the final linewidth definition.

Recently some Japanese lithographic equipment companies abandoned their immersion(liquid diffuses coherent light of dye laser) lens technology trying to compete with Polaroid filter technology. We are still exploring how fine(or smaller slits) is the limit of Polaroid filters in the world of lithography in the semiconductor industry. Masks are made by photographic equipment 30 feet away from a 10 foot drawing into half inch mask.

Semiconductor industry went thru dopant diffusion process epitaxial process and oxidation process by high temperature upto 1350 degrees C, thin film electron beam technology, and wet chemical oxidation and reduction processes. These technology never could do 100% yield of devices after hundreds of manufacturing steps.

We finally found the ideal ion deposition process. It uses ion accelerator at 5000 volts, back filled with argon gas. The source material is accelerated towards the target atom by atom, and can retain crystalline orientation and homogeneity.

The thickness of deposition is determined by time and voltage in a vacuum chamber. You can use pulses of voltage to make very thin deposition, and compound of source material can be deposited as well.

In more efficient ion depositors, sources can be rotated towards the target and deposit all different material to build up layers on the target sequentially. Target maybe vacuumed on the machine for quick installation and removal on the ion depositor.

Of course, each deposition of material will require lithography and removal of material for circuit elements in the final product.

The latest 12" wafer manufacturing plant now cost $3 billion for thousands(10/20) of wafer starts to batch process per week.

Cadence software creates a net list of standard 7400 cells by high level design language of circuit descriptions. It needs programmers to work as you imagine whatelse you need in your circuit. It is program as you go process. The net list connects each individual small circuit to achieve the desired functions using millions of transistors defined on the masks.

However, each silicon foundry uses different processing methods. The major ones are contact material(copper or aluminium), resistor material(nichrome or poly silicon) and gate material(silicon dioxide, zirconium oxide or hafnium nitride). So, the many hundreds of processing steps use different equipment, shaped by different masks step by step.

With ion deposition, many foundries will find the same way to make 7400 standard cells.

But Cadence software will remain leading edge, and usually require 100 programmers working full time to achieve a cpu project, programmed in one year. so, many new cpu designs are merely small additions of L2 cache. The architecture are very similar in the ix86 cpus.

We will find DSP cpu designs more interesting in the future. Mips may be used with large flash memory(internal or external apps) to do asic special functions(intant-on), programmable as you go?

Started in i486, there is the main 32 bit ALU core, then there is an 8 bit FPU core. the FPU is an 8 bit cisc with about 65,000 transistors even has its own L1 and L2 cache. It also has decimal point placement feature in the asic.

Pentiun4 has six FPUs, in addition to single or dual core ALU cores.

So, we have to learn how to do branch prediction for 8 bit registers to use L1 cache to mimic 32 bit ALU cores. It maybe easier to design FPU with risc instead of Cisc and have branch prediction asic built in.

Anyway, we still have to provide chip address and memory protection to run more than one core in the same time slice. i486 can only run either ALU or FPU alternately. To use both ALU and FPU at the same time L3 cache protected has to be used either internally or in the flash cards.

This development needs substantial rethinking on the operating system design? FPU can be programmed to manage data transfer to different cores? FPU can be programmed to run small tasks itself? FPU can do analog data with decimal numbers and analog data compression tables? Its the beginning of massive integration of functions in simultaneous data processing. 8 bit data processing uses less memory, but massive parallel processing can save time.

Lithography machines are steppers or wafer scale projection of mask on photo resist. Submicron started with 0.8 micron back in the early 1980s. Then 0.5, 0.4/0.35, 0.25, 0.18. 0.13, 0.09, 0.065, and now 0.045. 0.032 is now on the table.

Initially, lithographic machines use arc lamps down to 0.5 micron linewidth. Then, smart people started to think that photography of linewidth is a function of wavelength. So, dye laser of shorter wavelength is used. Now at 193 angstrom.

The reality is that arc lamps are too bright. dye laser is less bright which works better with thin and more sensitive photo resist. Spectrum and linewidth have no laws in physics that support the wavelength/slit size theory. Mask linewidth lets the clusters of gamma ray particles thru. A prism lets white light bend into different cluster of particles into what we call colors. Size of the clusters of gamma ray particles defines the colors. But each particle is free of the other, law of particle theory rather than law of wave theory holds.

So, 193 nm dye lasers can be moved back to reduce the light output intensity(distance to the fourth power), and masks will allow the specific clusters of particles to pass thru the linewidth of slits.

No one had to use X-ray to run finer lithography machines. But Polaroid filters increased yield of semiconductor devices by reducing defraction of light thru the mask..

But back in the late 1990s Intel R&D in Hillsboro, Ore announced the feasibility of 0.002 micron and MIT Lincoln lab announced 0.003 achieved. So, in year 2002, we have 4 inch diameter wafer scaled computer of DSPs built on 0.003 micron lithography machines. However, due to power supply considerations, the isolation line width was 0.130 micron to sustain 1.2 volt capabilty. But no amount of cooling can run the wafer scale computers indefinitely. The core voltage was dropped to 0.17 volts in 2005. Then in 2008, into microvolts for operating voltage design to run without cooling.

When the working voltage decreased, the heating up problems disappeared. The active device area can be increased. 0.002 can support 0.02 volt, but run at anything lower than 0.01 volt.

So, for now, we will be staying at 0.002 micron lithography until the commercial semi industry catches up.